1. Technical Field
The present application relates to a liquid crystal display device, and more particularly, to a driving method of a liquid crystal display device.
2. Related Art
A liquid crystal display (LCD) device 100, as shown in FIG. 1, includes an interface circuit 101, a timing controller 102, a gate driver 103, a source driver 104, a LCD panel 105, an inverter 106 and a backlight unit 107. If data is supplied from a computer graphics card or the like, the interface circuit 101 generates various signals: for example, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal and a data clock signal, and transmits these signals to the timing controller 102.
The timing controller 102 generates a control signal for the gate driver 103 and the source driver 104 based on a signal provided from the interface circuit 101, and transmits the control signals to the gate driver 103 and the source driver 104. The control signal transmitted to the gate driver 103 from the timing controller 102 is called a Gate Start Pulse (GSP) and marks a point in time at which a first gate line of a screen is turned-on. The gate line is turned on for a period of one data frame during which the Vsync signal is applied.
The control signal for the gate driver 103 includes a Gate Shift Clock (GSC) and a Gate Output Enable (GOE). The GSC determines a time at which gates of a plurality of thin-film transistors (TFTs) of the LCD panel 105 are turned-on or off, and the GOE controls an output of the gate driver 103.
The control signal, transmitted to the source driver 104 from the timing controller 102, is a Source Start Pulse (SSP) marking a data start time point for the Hsync signal, which is the time at which data is applied to the first source line. The control signal transmitted to the source driver 104 includes a Source Shift Clock (SSC) and a Source Output Enable (SOE). The SSC marks a time for driving the source driver 104, and the SOE determines an output of the source driver 104.
That is, the GSP, the GSC, and the GOE of the control signal generated from the timing controller 102 are provided to the gate driver 103. The SSP, the SSC and the SOE of the control signal generated from the timing controller 102 are provided to the source driver 104.
The gate driver 103 sequentially supplies a scan pulse of a gate high voltage to gate lines according to the GSC provided from the timing controller 102 to transfer data to a liquid crystal cell of the LCD panel 105. The source driver 104 latches data according to the SSP, the SSC and the SOE provided from the timing controller 102 to provide the latched data to the source lines.
The gate lines are sequentially driven to turn on the thin-film transistor of the LCD panel 105 and at the same time, the latched data is transferred to the LCD panel 105. Each pixel electrode has a voltage difference with respect to a common electrode associated with the applied voltage. This voltage difference for each pixel determines the transmission characteristics for each pixel and permits the LCD to display the information provided by the graphics controller, or other data source.
LCD panels do not generally incorporate a source of illumination, information is displayed by reflecting external light traversing the LCD panel 105, or information is displayed by transmitting light generated by a backlight unit 107 having a separate light source, which may be one or more lamps. The former is called a reflective liquid crystal display device, and the latter is called a transmissive liquid crystal display device. If a backlight unit is used it is installed at a rear surface or side surface of the LCD panel 105.
In a high-brightness or large-size liquid crystal display device, the transmissive liquid crystal display device typically employs a direct-type backlight unit where the light source is installed at the rear surface of the LCD panel 105, rather than an edge type backlight unit where the light source is installed at the side surface of the LCD panel 105.
The direct type backlight unit 107 shown in FIG. 2 includes a plurality of lamps 109 arrayed in an array behind the LCD panel 105 to light LCD panel when the lights are turned on. The duration of the illumination is determined by the Vsync signal from the interface circuit 101.
One method of driving the plurality of lamps constituting the direct type backlight unit is a collective-lighting blink backlight method in which the plurality of lamps are collectively turned on during the Vsync period. Another method is a scan backlight method in which the lamps are turned on sequentially beginning from the top most lamp.
FIGS. 3 and 4 are views illustrating the blink backlight method and the scan backlight method, respectively. In the blink backlight method of FIG. 3, the plurality of lamps are turned on and off collectively. In the scan backlight method of FIG. 4, the plurality of lamps are turned on and off sequentially.
In case where the scan backlight method is employed, the plurality of lamps 107 of the backlight unit of FIG. 1 should be turned on and off sequentially during each period for which data is applied. To do this, the backlight unit 107 provides the Vsync signal from the interface circuit 101 to the inverter 106. The inverter 106 determines the on/off duration for the plurality of lamps of the backlight unit 107 depending on the Vsync signal such that a power source (not shown) is applied to the lamp for a predetermined duration. Accordingly, in the backlight unit 107, the lamps are sequentially turned on by the vertical synchronous signal.
The scan pulse of the gate driver 103 and the data of the source driver 104 are provided to the LCD panel 105 depending on the GSP and the SSP.
Referring to FIG. 5, the timing controller 102 generates the GSP, the GSC and the GOE by using the Vsync signal, and generates the SSP, the SSC and the SOE by using the Hsync signal. The GSP, the GSC and the GOE are provided to the gate driver 103, and the SSP, the SSC and the SOE are provided to the source driver 104. The GSP and the SSP are at a predetermined time intervals with respect to the start time of the Vsync signal.
The gate driver 103 applies the scan pulse to the first gate line depending on the GSP and, though not illustrated in FIG. 5, continues to sequentially apply the scan pulse to second, third, . . . , nth gate lines. Whenever the scan pulse is sequentially applied to the gate lines, pixel data are applied to the source lines.
That is, the source driver 104 applies data to the first source line depending on the SSP and at the same time, collectively applies data to the second, third, . . . , nth source lines.
Thus, the LCD panel 105 receives data from each of the source lines being intersected at the first gate line, so as to charge a pixel capacitor to a voltage corresponding to a gray scale value.
After the lapse of a predetermined pixel capacitor charging time, a voltage corresponding to a desired grayscale is present across the pixel capacitance. During the pixel charging time, information is not perfectly displayed on a corresponding pixel, as the voltage is varying. When the pixel capacitor is fully charged, the transmission properties of the liquid crystal of the pixel are controlled on the basis of the voltage difference between the pixel electrode and the common electrode, so as to display the desired gray scale value.
Alternatively, when the scan backlight method is used, the plurality of lamps employing are sequentially turned on and off, beginning from the top to the bottom of the LCD panel, depending on the Vsync signal. Specifically, the first lamp of the scan backlight is synchronized to the vertical synchronous signal to be turned on for a predetermined time at the start time of the Vsync signal.
As such, the related-art liquid crystal display device has a drawback in that a turn-on time point of the lamp leads, by a predetermined time, a time point at which the scan pulse and data are applied by the GSP and the SSP, thereby reducing the power consumption efficiency of backlight unit and the display fidelity.